1. Field of the Invention
The present invention relates to a semiconductor integrated circuit outputting an output signal based on an internal power supply voltage, in particular, an output or bidirectional buffer circuit which tolerates an external input voltage that is higher than the internal power supply voltage. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-69479 filed on Mar. 11, 2004, which is herein incorporated by reference.
2. Description of the Related Art
A system Large Scale Integration circuit (hereinafter referred to as “LSI”) is composed of a plurality of semiconductor integrated circuits. Since an area of one semiconductor chip on which the semiconductor integrated circuits are disposed is limited, there may be power supply voltages different from each other with respect to a signal interface between the semiconductor integrated circuits. Therefore, when the semiconductor integrated circuits which respectively operate with different power supply voltages (for example, 3V and 5V) are coupled with each other, the semiconductor integrated circuit which operates with a lower power supply voltage may require a signal interface which can correspond to the semiconductor integrated circuit which operates with a higher power supply voltage. On such an occasion as this, the semiconductor integrated circuit which operates with the lower power supply voltage may commonly use a tolerant input-output circuit, which is capable of receiving the higher power supply voltage externally, as the signal interface. Alternatively, the semiconductor integrated circuit which operates with the lower power supply voltage may commonly use a tolerant input-output circuit, which can pull up the low power supply voltage, as the signal interface.
In a Patent Document 1 (Japanese Patent Publication Laid-open No. 2000-196436), an input-output circuit has a diode-connected PMOS transistor 11 and a P-conductive type MOS (hereinafter referred to as “PMOS”) transistor 12 as an output transistor and a protection transistor which are coupled in series between an internal electrical source terminal and an output terminal PAD, and the PMOS transistor 12 has an electrically floating well of a semiconductor substrate. That is, the Document 1 shows that an electrical current, caused by an external power supply voltage which is higher than the internal power supply voltage, is prevented from flowing constantly from the output terminal into the internal electrical source terminal by turning the PMOS transistor 12 OFF when the external voltage is applied to the output terminal PAD.
On the other hand, an input-output circuit has an output PMOS transistor 7 coupled between an internal electrical source terminal and an output terminal in a Patent Document 2 (Japanese Patent Publication Laid-open No. Hei 10-163852). In Document 2, after the input-output circuit is disabled [disenable] with the electrical potential of the output terminal being kept at the “H” level, the output terminal receives an external power supply voltage higher than the internal power supply voltage. In this instance, an electrical potential of a gate electrode of the output PMOS transistor 7 is changed from a ground voltage to the external power supply voltage through the internal power supply voltage. When the gate electrode of the output PMOS transistor 7 is changed from the internal power supply voltage to the external power supply voltage, a tolerant control circuit operates using an external current caused by the external power supply voltage.
However, since the input-output circuit of the Document 1 has the two PMOS transistors coupled in series, the input-output circuit requires double or more usual sizes of the PMOS transistors 11 and 12 in order to realize a desired power of driving and its characteristics of rise time and fall time when the input-output circuit is used as an output circuit. That is, the input-output circuit described in the Document 1 requires a greater area on which the PMOS transistors are formed. Also, in the input-output circuit of the Document 2, until the output PMOS transistor 7 receives the internal power supply voltage after receiving the ground voltage, the external current substantially flows into the output PMOS transistor 7. That is, an electrical potential of the output terminal can not be promptly pulled up by the external power supply voltage until the output PMOS transistor 7 is turned OFF. Therefore, it takes a few seconds or more time than usual to pull up the electrical potential of the output terminal, which is increased by an external resistance and a parasitic capacitance. On such an occasion as this, the external current which ranges from several microamperes to several ten microamperes passes through the output PMOS transistor 7 during a few milliseconds. As a result, electrical power consumption in the input-output circuit may be increased.